Exception causes the CPU core enter into a specific mode. In addition, by altering the cpsr also CPU core can (manually) enter into to any specific modes of ARM processor.
To enter into user and system mode we must need to modify the cpsr, there are only two modes are not enters by a corresponding exception.
When an exception occurs, below are things happens automatically by the core:
saves the cpsr to the spsr of the exception mode
saves the pc to the lr of the exception mode.
Please find below picture representation of exceptions and its corresponding modes,
- Reset vector is the location of first instruction runs by the cpu when power is applied. This instruction branches to the initialization code.
- When we execute a SWI instruction (system call), software interrupt vector will be called, then specific system call method operation will be performed.
- When the processor attempts to fetch an instruction from an address with incorrect access permissions, prefetch abort vector will occurs. In the decode stage, the actual abort will occurs
- Data abort vector is same as a prefetch abort but is occurs when an instruction attempts to access data memory without the correct access permissions.
- When the processor cannot able to decode an instruction, undefined instruction vector will occurs.